SLIM-DDS-107 rev D
DDS with Squarer
5-14-15. Modify and change Schematic to Rev E.
Change Parts List from Rev D to Rev E and move to this web page.
1-13-16. Modify and change Parts List to Rev F
Direct Digital Synthesizer,
Use your mouse's "right click" and "Save Link" to download:
Schematic, in ExpressPCB software.
b. PWB-DDS Rev C
Base artwork for PWB, in ExpressPCB software.
Use this drawing to order the pwb from Express, or to locate
the parts on the Board.
List. Maintained only on this page.
designed and configured with a
filter and squaring circuit in the DDS A path. The
filter shown is
10.7 MHz with a 15 KHz bandwidth. The squaring circuit
of U3 will output a
CMOS level, capable of driving a 50 ohm line (J4). J2 is not used
when the squaring circuit is configured. J3 output is an
the DDS B and will contain all harmonics and aliases of a normal DDS
output. Its output power level is approximately -8 dBm.
For best results, the Clock Input at J1 should be a
5 volt peak
to peak square wave, but it will operate at a much lower input.
R3 determines the input impedance of the
module. It can be removed for a high impedance input, or changed
to any value. The input clock frequency must be between 1 MHz and
125 MHz, although the AD9850 is somewhat underrated.
The DDS module was originally designed for parallel
commanding. Serial commanding is accomplished by modifying the
connector, P1. The modification is thus:
Connect P1-3 to P1-6 This creates a "1" on BD0 and
Connect P1-4 to P1-5,10,11, and 12 This
creates a "0" on BD2, BD3, BD4, BD5, and BD6.
This leaves pin 9, BD7 (P1-9) to be serially driven, along with
WCLK (P1-7) and
The resistors R11 and
R12 do not interfere with parallel commanding, because BD1 and BD2 are
driven by a "hard" signal.
The AD9851 is an
optional replacement for the AD9850. Its clock rate limit
is 180 MHz. It has an internal clock multiplier of x6. It
is not advertised nor guaranteed, but the AD9850 also has an internal
clock multiplier of x4.
SK-DDS-107, Schematic, Revision E